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Push-Pull FET Driver with Integrated Oscillator
and Programmable Clock Output
Applications Information
Supply Bypassing
Pay careful attention to bypassing and grounding the
MAX5077. Peak supply and output currents may exceed
3A when driving large MOSFETs. Ground shifts due to
insufficient device grounding may also disturb other cir-
cuits sharing the same ground-return path. Any series
inductance in the V CC , NDRV1, NDRV2, and/or GND
paths can cause noise due to the very high di/dt when
switching the MAX5077 with any capacitive load. Place
one or more 0.1μF ceramic capacitors in parallel as
close to the device as possible to bypass V CC to PGND.
Use a ground plane to minimize ground-return resis-
tance and inductance. Place the external MOSFETs as
close as possible to the MAX5077 to further minimize
board inductance and AC path impedance.
Power Dissipation
Power dissipation of the MAX5077 is a function of the
sum of the quiescent current and the output current
(either capacitive or resistive load). Maintain the sum of
the currents so the maximum power dissipation limit is
not exceeded. The power dissipation (P DISS ) due to the
quiescent switching supply current (I CCSW ) can be cal-
culated as:
P DISS = V CC x I CCSW
For capacitive loads, use the following equation to esti-
mate the power dissipation:
P LOAD = 2 x C LOAD x V CC 2 x f NDRV_
where C LOAD is the capacitive load at NDRV1 and
NDRV2, V CC is the supply voltage, and f NDRV_ is the
MAX5077 NDRV_ switching frequency.
Calculate the total power dissipation (P T ) as follows:
P T = P DISS + P LOAD
Layout Recommendations
The MAX5077 drivers source and sink large currents
that can create very fast rise and fall edges at the gate
of the switching MOSFETs. The high di/dt can cause
unacceptable ringing if the trace lengths and imped-
ances are not well controlled. Use the following PC
board layout guidelines when designing with the
MAX5077:
? Place one or more 0.1μF decoupling ceramic capac-
itors from V CC to PGND as close to the device as
possible. Connect V CC and all ground pins to large
copper areas. Place one bulk capacitor of 10μF on
the PC board with a low-impedance path to the V CC
input and PGND of the MAX5077.
? Two AC current loops form between the device and
the gates of the driven MOSFETs. The MOSFET looks
like a large capacitance from gate to source when the
gate pulls low. The current loop is from the MOSFET
gate to NDRV1/NDRV2 of the MAX5077, to PGND, and
to the source of the MOSFETs. When the gate of the
MOSFET is pulled high, the current is from the V CC ter-
minal of the decoupling capacitor, to V CC of the
MAX5077, to NDRV1/NDRV2, to the MOSFET gate and
source. Both charging current and discharging current
loops are important. Minimize the physical distance
and the impedance in these AC current paths.
? Keep the device as close to the MOSFET as possible.
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